The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each new generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs.
During the scaling trend, various materials have been used for the gate electrode and gate dielectric in field effect transistors (FET). One approach is to fabricate these devices with a metal material for the gate electrode and a high-k dielectric for the gate dielectric. However, high-k metal gate (HKMG) devices often require additional layers in the gate structure. For example, work function layers may be used to tune the work function values of the metal gates. Although these approaches have been generally adequate for their intended purposes, they have not been satisfactory in all respects. For example, each additional layer in the HKMG gate stack may reduce the thickness of the upper-most metal layer in the stack, increasing the difficulty of device fabrication. This issue is particularly relevant to analog HKMG devices, which may have thicker gate dielectric layers. Furthermore, HKMG devices may suffer from a power short circuit issue resulting from a contact etch through the gate stack.